This invention relates to level shift means for interfacing logic circuits having dissimilar logic voltage levels.
In many digital systems, the need arises to interconnect logic elements from different logic families or to interconnect logic elements operated at different supply potentials. For example, to connect a transistor-transistor logic element (TTL) output to a complementary symmetry metal oxide semiconductor (CMOS) logic element input, an interface circuit is required to shift from the TTL logic levels (typically 0.8 to 2.4 volts) to the CMOS logic levels (typically 0 to 10 volts).
A common problem that many prior art level shift circuits share is that the rise and fall times of the output signal are unequal. Furthermore, propagation delays from input to output are unequal for high-to-low and low-to-high transitions. In a typical case, one edge of the level shifted signal, say the rising edge, will have a relatively slow rise time and long propagation delay. However, the falling edge will have a relatively fast fall time and correspondingly short propogation delay. Such unsymmetrical circuit response introduces signal overlap between concurrent logic signals which changes their timing relationship. Timing changes between logic signals, particularly in the case of control signals or clock signals, has an adverse effect on system operation.
Prior art attempts to equalize the level shifter response for output transitions in both directions involves the use of active pull-up and pull-down devices with controlled inputs for waveshaping the output signal. Such circuits tend to be complex and do not lead themselves to fabrication in digital integrated circuit form.